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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Georgia",serif;color:blue">Your understanding is exactly correct.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Georgia",serif;color:blue"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Georgia",serif;color:blue">-Jon<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Georgia",serif;color:blue"><o:p> </o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> Wang, Huibo <Huibo.Wang@amd.com>
<br>
<b>Sent:</b> Friday, December 6, 2024 11:06 AM<br>
<b>To:</b> Jon Lange <jlange@microsoft.com><br>
<b>Cc:</b> svsm-devel@coconut-svsm.dev; Joerg Roedel <jroedel@suse.de>; Lendacky, Thomas <Thomas.Lendacky@amd.com><br>
<b>Subject:</b> [EXTERNAL] Re: Alternate Injection spec question<o:p></o:p></span></p>
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</div>
<p class="MsoNormal"><o:p> </o:p></p>
<p style="margin:5.0pt"><span style="font-size:10.0pt;font-family:"Calibri",sans-serif;color:blue">[AMD Official Use Only - AMD Internal Distribution Only]<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="color:black">Hi Jon,<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="color:black"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="color:black">Ok, I understand. Thank you. This is how I understand the handoff process should take place. Can you please confirm my understanding?<o:p></o:p></span></p>
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<li class="MsoNormal" style="color:black;mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;mso-list:l0 level1 lfo1">
The SVSM will start with the Alternate Injection enabled or not by having the knowledge from firmware, if it is enabled, then the registration count becomes 1, otherwise Alternate Injection will not be enabled.<o:p></o:p></li></ol>
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<li class="MsoNormal" style="color:black;mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;mso-list:l0 level1 lfo1">
Prior to the executing exit_boot_services, the guest OS will detect if the Alternate Injection is enabled or not, then if it is enabled, the guest OS will determine if it wants to enable Alternate Injection, if it does, it will register, thus the count will
increment, otherwise, it will not register. <o:p></o:p></li></ol>
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<li class="MsoNormal" style="color:black;mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;mso-list:l0 level1 lfo1">
The firmware will deregister itself during exit_boot_services, here the count will be reduced to 1/0, depending on if the guest OS registers or not. If the guest OS registered itself, then the count would be 1, the Alternate Injection is enabled, if the count
is 0, then the SVSM will disable Alternate Injection. <o:p></o:p></li></ol>
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<p class="MsoNormal"><span style="color:black">Thanks,<o:p></o:p></span></p>
</div>
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<p class="MsoNormal"><span style="color:black">Melody<o:p></o:p></span></p>
</div>
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<p class="MsoNormal"><span style="color:black"><o:p> </o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black"> Jon Lange <<a href="mailto:jlange@microsoft.com">jlange@microsoft.com</a>><br>
<b>Sent:</b> Thursday, December 5, 2024 4:40 PM<br>
<b>To:</b> Wang, Huibo <<a href="mailto:Huibo.Wang@amd.com">Huibo.Wang@amd.com</a>><br>
<b>Cc:</b> <a href="mailto:svsm-devel@coconut-svsm.dev">svsm-devel@coconut-svsm.dev</a> <<a href="mailto:svsm-devel@coconut-svsm.dev">svsm-devel@coconut-svsm.dev</a>>; Joerg Roedel <<a href="mailto:jroedel@suse.de">jroedel@suse.de</a>>; Lendacky, Thomas <<a href="mailto:Thomas.Lendacky@amd.com">Thomas.Lendacky@amd.com</a>><br>
<b>Subject:</b> RE: Alternate Injection spec question</span> <o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="xmsonormal"><span style="font-size:10.0pt;font-family:"Georgia",serif;color:blue">The language from the spec says the following:</span><o:p></o:p></p>
<p class="xmsonormal"><span style="color:black">The SVSM is required to have knowledge of whether the first component that executes can support the Alternate Injection protocol.</span><o:p></o:p></p>
<p class="xmsonormal"><span style="font-size:10.0pt;font-family:"Georgia",serif;color:blue"> </span><o:p></o:p></p>
<p class="xmsonormal"><span style="font-size:10.0pt;font-family:"Georgia",serif;color:blue">I thought “required to have knowledge” would be clear. What additional information are you hoping to see in the spec?</span><o:p></o:p></p>
<p class="xmsonormal"><span style="font-size:10.0pt;font-family:"Georgia",serif;color:blue"> </span><o:p></o:p></p>
<p class="xmsonormal"><span style="font-size:10.0pt;font-family:"Georgia",serif;color:blue">-Jon</span><o:p></o:p></p>
<p class="xmsonormal"><span style="font-size:10.0pt;font-family:"Georgia",serif;color:blue"> </span><o:p></o:p></p>
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<div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in">
<p class="xmsonormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> Wang, Huibo <<a href="mailto:Huibo.Wang@amd.com">Huibo.Wang@amd.com</a>>
<br>
<b>Sent:</b> Thursday, December 5, 2024 1:20 PM<br>
<b>To:</b> Jon Lange <<a href="mailto:jlange@microsoft.com">jlange@microsoft.com</a>><br>
<b>Cc:</b> <a href="mailto:svsm-devel@coconut-svsm.dev">svsm-devel@coconut-svsm.dev</a>; Joerg Roedel <<a href="mailto:jroedel@suse.de">jroedel@suse.de</a>>; Lendacky, Thomas <<a href="mailto:Thomas.Lendacky@amd.com">Thomas.Lendacky@amd.com</a>><br>
<b>Subject:</b> [EXTERNAL] Re: Alternate Injection spec question</span><o:p></o:p></p>
</div>
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<p class="xmsonormal"> <o:p></o:p></p>
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<p class="xmsonormal"><span style="color:black">Hi Jon,</span><o:p></o:p></p>
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<p class="xmsonormal"><span style="color:black"> </span><o:p></o:p></p>
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<p class="xmsonormal"><span style="color:black">Thanks a lot, perhaps the spec should be extended with that info as it is not obvious at the moment. </span><o:p></o:p></p>
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<p class="xmsonormal"><span style="color:black"> </span><o:p></o:p></p>
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<p class="xmsonormal"><span style="color:black">Thanks,</span><o:p></o:p></p>
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<p class="xmsonormal"><span style="color:black">Melody</span><o:p></o:p></p>
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<p class="xmsonormal"><span style="color:black"> </span><o:p></o:p></p>
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<p class="xmsonormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black"> Jon Lange <<a href="mailto:jlange@microsoft.com">jlange@microsoft.com</a>><br>
<b>Sent:</b> Wednesday, December 4, 2024 9:01 PM<br>
<b>To:</b> Wang, Huibo <<a href="mailto:Huibo.Wang@amd.com">Huibo.Wang@amd.com</a>><br>
<b>Cc:</b> <a href="mailto:svsm-devel@coconut-svsm.dev">svsm-devel@coconut-svsm.dev</a> <<a href="mailto:svsm-devel@coconut-svsm.dev">svsm-devel@coconut-svsm.dev</a>>; Joerg Roedel <<a href="mailto:jroedel@suse.de">jroedel@suse.de</a>>; Lendacky, Thomas <<a href="mailto:Thomas.Lendacky@amd.com">Thomas.Lendacky@amd.com</a>><br>
<b>Subject:</b> RE: Alternate Injection spec question</span> <o:p></o:p></p>
<div>
<p class="xmsonormal"> <o:p></o:p></p>
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<p style="margin:5.0pt"><span style="font-size:10.0pt;font-family:"Calibri",sans-serif;color:blue">[AMD Official Use Only - AMD Internal Distribution Only]</span><o:p></o:p></p>
<p class="xmsonormal"> <o:p></o:p></p>
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<p class="xxmsonormal"><span style="font-size:10.0pt;font-family:"Georgia",serif;color:blue">Melody,</span><o:p></o:p></p>
<p class="xxmsonormal"><span style="font-size:10.0pt;font-family:"Georgia",serif;color:blue"> </span><o:p></o:p></p>
<p class="xxmsonormal"><span style="font-size:10.0pt;font-family:"Georgia",serif;color:blue">As stated in the spec, Alternate Injection can only provide strong security guarantees if it is active from the first instruction of the guest firmware. This means
that the firmware cannot negotiate the use of Alternate Injection – it must already be active by the time firmware starts executing. The expectation is that there is a strong coupling between the SVSM image and the firmware image – after all, the initial
launch measurements always include both, so it is reasonable to assume that the SVSM has knowledge of how the embedded firmware is going to operate. Therefore, the SVSM must be configured to configure Alternate Injection based on the design of the firmware.
If the firmware is capable of using Alternate Injection, then the SVSM should configure the initial guest VMSA to enable Alternate Injection. Any firmware image that is capable of using Alternate Injection should be smart enough to read SEV_FEATURES to detect
whether it is enabled and to call the SVSM to disable Alternate Injection if it doesn’t want the feature enabled. On the other hand, if the firmware is not capable of using Alternate Injection, then the SVSM should create the initial guest VMSA without enabling
Alternate Injection.</span><o:p></o:p></p>
<p class="xxmsonormal"><span style="font-size:10.0pt;font-family:"Georgia",serif;color:blue"> </span><o:p></o:p></p>
<p class="xxmsonormal"><span style="font-size:10.0pt;font-family:"Georgia",serif;color:blue">To put it another way, more closely related to the spec language, the SVSM is supposed to know what the “first component” is, and what that first component expects,
and the SVSM is supposed to be built with that configuration in mind.</span><o:p></o:p></p>
<p class="xxmsonormal"><span style="font-size:10.0pt;font-family:"Georgia",serif;color:blue"> </span><o:p></o:p></p>
<p class="xxmsonormal"><span style="font-size:10.0pt;font-family:"Georgia",serif;color:blue">Regarding INIT/SIPI – I think you are correct; the spec is missing the word “not”. INIT/SIPI should only be used by the guest if it knows that the SVSM APIC supports
INIT/SIPI.</span><o:p></o:p></p>
<p class="xxmsonormal"><span style="font-size:10.0pt;font-family:"Georgia",serif;color:blue"> </span><o:p></o:p></p>
<p class="xxmsonormal"><span style="font-size:10.0pt;font-family:"Georgia",serif;color:blue">-Jon</span><o:p></o:p></p>
<p class="xxmsonormal"><span style="font-size:10.0pt;font-family:"Georgia",serif;color:blue"> </span><o:p></o:p></p>
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<div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in">
<p class="xxmsonormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> Wang, Huibo <<a href="mailto:Huibo.Wang@amd.com">Huibo.Wang@amd.com</a>>
<br>
<b>Sent:</b> Tuesday, December 3, 2024 10:20 PM<br>
<b>To:</b> Jon Lange <<a href="mailto:jlange@microsoft.com">jlange@microsoft.com</a>><br>
<b>Cc:</b> <a href="mailto:svsm-devel@coconut-svsm.dev">svsm-devel@coconut-svsm.dev</a>; Joerg Roedel <<a href="mailto:jroedel@suse.de">jroedel@suse.de</a>>; Lendacky, Thomas <<a href="mailto:Thomas.Lendacky@amd.com">Thomas.Lendacky@amd.com</a>><br>
<b>Subject:</b> [EXTERNAL] Re: Alternate Injection spec question</span><o:p></o:p></p>
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<p class="xxmsonormal"> <o:p></o:p></p>
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<p style="margin:5.0pt"><span style="font-size:10.0pt;font-family:"Calibri",sans-serif;color:blue">[AMD Official Use Only - AMD Internal Distribution Only]</span><o:p></o:p></p>
<p class="xxmsonormal"> <o:p></o:p></p>
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<p class="xxmsonormal"><span style="color:black">Hi Jon, </span><o:p></o:p></p>
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<p class="xxmsonormal"><span style="color:black"> </span><o:p></o:p></p>
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<p class="xxmsonormal"><span style="color:black">I have a couple questions about the spec. </span><o:p></o:p></p>
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<p class="xxmsonormal"><span style="color:black"> </span><o:p></o:p></p>
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<p class="xxmsonormal"><span style="color:black">1. For the mechanism transferring control from guest firmware to guest OS, <br>
from the flow I read, I wonder how the firmware (first component) can<br>
register the use of Alternate Injection.<br>
<br>
I see there are 3 forms of the SVSM_APIC_CONFIGURE_EMULATION call:<br>
<br>
1. ECX[1:0] = 0b00, disable Alternate Injection if reg count == 0<br>
2. ECX[1:0] = 0b01, deregister the guest, if reg_count == 0, disable AI<br>
3. ECX[1:0] = 0b10, register the guest, no change to AI setting<br>
<br>
So how does the firmware (first component) register? Or, could you help me<br>
understand how do you envision this process to happen?<br>
<br>
There's text related to that in the beginning of the spec:<br>
<br>
"The SVSM is required to have knowledge of whether the first component that<br>
executes can support the Alternate Injection protocol. If the SVSM does not<br>
know that the first component to execute will support the SVSM APIC Protocol,<br>
then it must not enable Alternate Injection in the guest VMSA. If the SVSM<br>
does know that the first component to execute will support the SVSM APIC<br>
Protocol, then it will enable Alternate Injection prior to the first guest<br>
entry; the first guest component must either make use of the protocol or it<br>
must request that the protocol be disabled."<br>
<br>
I *think* this "make use of the protocol" is how you want the SVSM to detect<br>
that the first component is going to use AI and I think that "make use" is by<br>
doing SVSM_APIC_CONFIGURE_EMULATION but as far as I'm reading it, I can't find<br>
an ECX[1:0] setting which says, "I'm the first component, I'm going to use<br>
AI"?<br>
<br>
Or do you mean the first component should use some other SVSM APIC protocol<br>
call like SVSM_APIC_QUERY_FEATURES, for example?<br>
<br>
2. In SVSM APIC Protocol - Query Features section, <br>
<br>
"Bit 1 indicates support for INIT and SIPI delivery. If INIT and SIPI<br>
delivery are not supported, the guest may use INIT and SIPI signals to<br>
start additional vCPUs within the invoking VMPL. Note that even if INIT<br>
and SIPI are supported, the guest must still use the VMSA creation calls of<br>
the SVSM Core Protocol to start additional vCPUs so that the Calling Area<br>
address for each vCPU can be configured correctly."<br>
<br>
Is it possible that the marked here means "may not use" instead of "may use"?</span><o:p></o:p></p>
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<p class="xxmsonormal"><span style="color:black"> </span><o:p></o:p></p>
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<pre><span style="font-size:12.0pt;font-family:"Aptos",sans-serif;color:black">Thanks,</span><o:p></o:p></pre>
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<pre><span style="font-size:12.0pt;font-family:"Aptos",sans-serif;color:black">Melody</span><o:p></o:p></pre>
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<p class="xxmsonormal"><span style="color:black"> </span><o:p></o:p></p>
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<p class="xxmsonormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black"> Wang, Huibo<br>
<b>Sent:</b> Wednesday, November 13, 2024 5:42 PM<br>
<b>To:</b> Jon Lange <<a href="mailto:jlange@microsoft.com">jlange@microsoft.com</a>><br>
<b>Cc:</b> <a href="mailto:svsm-devel@coconut-svsm.dev">svsm-devel@coconut-svsm.dev</a> <<a href="mailto:svsm-devel@coconut-svsm.dev">svsm-devel@coconut-svsm.dev</a>>; Joerg Roedel <<a href="mailto:jroedel@suse.de">jroedel@suse.de</a>>; Lendacky, Thomas <<a href="mailto:Thomas.Lendacky@amd.com">Thomas.Lendacky@amd.com</a>><br>
<b>Subject:</b> Alternate Injection spec question</span> <o:p></o:p></p>
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<p class="xxmsonormal"><span style="font-size:11.0pt">Hi Jon,<br>
<br>
Yeah, the one I have is version of May, thank you for the update.<br>
<br>
Thanks<br>
Melody<br>
<br>
-----Original Message-----<br>
From: Jon Lange <<a href="mailto:jlange@microsoft.com">jlange@microsoft.com</a>><br>
Sent: Wednesday, November 13, 2024 5:23 PM<br>
To: Wang, Huibo <<a href="mailto:Huibo.Wang@amd.com">Huibo.Wang@amd.com</a>><br>
Cc: <a href="mailto:svsm-devel@coconut-svsm.dev">svsm-devel@coconut-svsm.dev</a>; Joerg Roedel <<a href="mailto:jroedel@suse.de">jroedel@suse.de</a>>; Lendacky, Thomas <<a href="mailto:Thomas.Lendacky@amd.com">Thomas.Lendacky@amd.com</a>><br>
Subject: RE: Svsm-devel Digest, Vol 10, Issue 19<br>
<br>
[AMD Official Use Only - AMD Internal Distribution Only]<br>
<br>
I think you have an old version of the spec. The latest version (attached) has all five calls.<br>
<br>
-Jon<br>
<br>
-----Original Message-----<br>
From: Wang, Huibo <<a href="mailto:Huibo.Wang@amd.com">Huibo.Wang@amd.com</a>><br>
Sent: Wednesday, November 13, 2024 12:32 PM<br>
To: Jon Lange <<a href="mailto:jlange@microsoft.com">jlange@microsoft.com</a>><br>
Cc: <a href="mailto:svsm-devel@coconut-svsm.dev">svsm-devel@coconut-svsm.dev</a>; Joerg Roedel <<a href="mailto:jroedel@suse.de">jroedel@suse.de</a>>; Lendacky, Thomas <<a href="mailto:Thomas.Lendacky@amd.com">Thomas.Lendacky@amd.com</a>><br>
Subject: [EXTERNAL] RE: Svsm-devel Digest, Vol 10, Issue 19<br>
<br>
[You don't often get email from <a href="mailto:huibo.wang@amd.com">huibo.wang@amd.com</a>. Learn why this is important at
<a href="https://aka.ms/LearnAboutSenderIdentification">https://aka.ms/LearnAboutSenderIdentification</a> ]<br>
<br>
[AMD Official Use Only - AMD Internal Distribution Only]<br>
<br>
Hi Jon,<br>
<br>
For SVSM APIC Protocol changes, there are 4 listed in the spec, SVSM_APIC_QUERY_FEATURES, SVSM_APIC_READ_REGISTER, SVSM_APIC_WRITE_REGISTER, SVSM_APIC_CONFIGURE_VECTOR. In the coconut svsm github, there is one more "const SVSM_REQ_APIC_CONFIGURE: u32 = 1",
should this one also be included in the spec?<br>
<br>
Thanks<br>
Melody<br>
<br>
-----Original Message-----<br>
From: Svsm-devel <<a href="mailto:svsm-devel-bounces@coconut-svsm.dev">svsm-devel-bounces@coconut-svsm.dev</a>> On Behalf Of
<a href="mailto:svsm-devel-request@coconut-svsm.dev">svsm-devel-request@coconut-svsm.dev</a><br>
Sent: Friday, May 17, 2024 12:09 AM<br>
To: <a href="mailto:svsm-devel@coconut-svsm.dev">svsm-devel@coconut-svsm.dev</a><br>
Subject: Svsm-devel Digest, Vol 10, Issue 19<br>
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Today's Topics:<br>
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1. RFC: Alternate Injection SVSM support (Jon Lange)<br>
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----------------------------------------------------------------------<br>
<br>
Message: 1<br>
Date: Fri, 17 May 2024 04:40:24 +0000<br>
From: Jon Lange <<a href="mailto:jlange@microsoft.com">jlange@microsoft.com</a>><br>
To: "<a href="mailto:amd-sev-snp@lists.suse.com">amd-sev-snp@lists.suse.com</a>" <<a href="mailto:amd-sev-snp@lists.suse.com">amd-sev-snp@lists.suse.com</a>>,<br>
"<a href="mailto:svsm-devel@coconut-svsm.dev">svsm-devel@coconut-svsm.dev</a>" <<a href="mailto:svsm-devel@coconut-svsm.dev">svsm-devel@coconut-svsm.dev</a>><br>
Subject: [svsm-devel] RFC: Alternate Injection SVSM support<br>
Message-ID:<br>
<<a href="mailto:DS7PR21MB352462BA31B209F93F296A17CAEE2@DS7PR21MB3524.namprd21.prod.outlook.com">DS7PR21MB352462BA31B209F93F296A17CAEE2@DS7PR21MB3524.namprd21.prod.outlook.com</a>><br>
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Content-Type: text/plain; charset="us-ascii"<br>
<br>
Attached is a specification I am proposing to handle support for Alternate Injection in SNP guests through the use of an SVSM. This document proposes changes to the AMD GHCB specification and to the AMD SVSM specification to enable the negotiation required
to make Alternate Injection work correctly.<br>
<br>
Support for this protocol will not be possible in KVM until KVM is able to include native support for multiple VMPLs with separate interrupt sources for each. That work is underway elsewhere, and my expectation is that this proposed specification will align
with the capabilities that KVM will be introducing as part of the multi-VMPL support.<br>
<br>
I will be submitting changes to COCONUT-SVSM to implement this protocol. I welcome all feedback to the spec, and will update the code to match whatever spec changes are agreed upon.<br>
<br>
-Jon<br>
<br>
<br>
<br>
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